1. Field of the Invention
The present invention generally relates to a method for forming a gate dielectric layer of a thin film transistor, and more particularly, a method for forming a gate dielectric layer, in which the gate dielectric layer is formed by finely forming a plasma oxide layer by plasma and depositing an atomic layer deposition (ALD) oxide layer, thereby enhancing interfacial characteristics and decreasing current leakage.
2. Discussion of Related Art
In a display, particularly, in an active matrix type display, importance of a thin film transistor is large. To make a high performance display, the thin film transistor should have low current-leakage, high electron mobility, high on/off-currents ratio, and low threshold voltage. Such characteristics are swayed by a gate dielectric layer. That is, an interface state between the gate dielectric layer and silicon (or poly-silicon), and an internal defect, dopant, etc. of the gate dielectric layer have an effect on the performance of the thin film transistor.
In a recent display, a transparent glass substrate is employed for a backlight and a plastic substrate is also being tried in a future flexible display that can be bent or rolled up. In the case of the glass substrate, a fabricating process thereof needs a temperature of 600° C. or below. On the other hand, in the case of the plastic substrate, a fabricating process thereof needs a temperature of 200° C. or below.
Hitherto, the gate dielectric layer has been deposited on amorphous silicon or poly silicon, wherein silicon dioxide (SiO2) has been known as a material having a best interfacial characteristic for the gate dielectric layer, particularly, it is the most excellent when the silicon dioxide (SiO2) is formed by a thermal oxide layer.
However, in the case of the thermal oxide layer, a growth process thereof needs a high temperature of 800° C. or more, so that its actual application is difficult. Accordingly, there has been proposed a method of allowing the silicon dioxide (SiO2) to be characterized near the thermal oxide layer, using oxygen plasma at a low temperature.
In the case of using the oxygen plasma, a growth rate of the silicon dioxide (SiO2) is very low due to the low temperature and relatively much power is needed, so that it is difficult to form the gate dielectric layer, used in a display transistor having a thickness of 100 nm, as a single layer.
For example, there is a research that the silicon dioxide (SiO2) is grown on the poly silicon substrate by a plasma process to obtain an oxide layer near to the thermal oxide layer, wherein the oxide layer with a thickness of 10 nm is grown using a radio frequency (RF) power of 900 W at a temperature of 350° C. [IEEE Electron Device Letters, 23, pp 333 (2002)]. However, this research is carried out with respect to a 4-inch wafer, so that a relatively large 12-inch wafer needs nine times more power than that for the 4-inch wafer. Besides, its processing temperature is still high.
Here, the processing temperature can be lowered to a normal temperature when a physical deposition process such as ion plating or sputtering is used. However, the physical deposition process causes an interface to be damaged, thereby deteriorating the interfacial characteristic. Further, when the physical deposition process is applied to the relatively large wafer, uniformity is not good as compared with a chemical deposition process, so that it is difficult to actually utilize the physical deposition process.
Meanwhile, the chemical deposition process for depositing the silicon oxide layer includes an atmospheric pressure chemical vapor deposition (APCVD) process, a low pressure chemical vapor deposition (LPCVD) process, and a plasma enhanced chemical vapor deposition (PECVD) process. Here, the APCVD process using silane (SiH4) and oxygen (O2) is performed at a temperature of 400° C.˜450° C., and the silicon oxide layer deposition using inductively coupled plasma (ICP) is performed at a temperature of 400° C. [Applied Physics Letters, 74, pp 2693 (1999)].
However, such chemical deposition process is performed at a relatively high temperature, so that it cannot be applied to the plastic substrate. Further, when the chemical deposition process is applied to the relatively large wafer, not only the uniformity with regard to the relatively large wafer is not good, but also problems arise in reproducibility and reliability.
To solve the above-mentioned problems, there has been being researched a method of forming the silicon oxide layer using an atomic layer deposition (ALD) process. In the ALD process, a source is absorbed below a source decomposition temperature, and reaction gas is introduced to induce surface reaction, thereby depositing a thin film. Thus, the ALD process is performed below the source decomposition temperature, so that the uniformity with regard to the relatively large wafer is good, and the reproducibility and the reliability are relatively excellent.
Currently, plasma is used to enhance reactivity of the reaction gas, thereby fabricating a good thin film. For example, there is a research as to zirconium dioxide (ZrO2) deposited by a plasma enhance atomic layer deposition (PEALD) process at a temperature of 250° C. [Journal of Applied Physics, 92, pp 5443 (2002)]. However, there is very little research as to the silicon dioxide (SiO2) deposited by on the PEALD process. Also, there is very little research as to the lower temperature deposition below 200° C. or less.
Further, an application of a high dielectric layer is being researched for a semiconductor gate dielectric layer, but a problem arises in compatibility with the silicon substrate, that is, an wanted interlayer may be formed an interface, or current leakage due to crystallization may be increased. Hence, there is needed a method of avoiding direct contact between the gate dielectric layer and the silicon substrate.